1. Field of the Invention
The present invention relates to comparator circuits. More specifically, the invention relates to a self-timed differential comparator for applications such as performing a fast comparison of multiple address signals.
2. Description of the Related Art
Microprocessor architectures are continually evolving to improve and extend the capabilities of personal computers. Execution speed, power consumption, and circuit size are aspects of microprocessors and microprocessor performance that are constantly addressed by processor architects and designers in the ongoing quest for an improved product. Execution speed not only depends on the clock rate of a processor, but also upon the speed of interfaces such as cache memories and buses that supply instructions and data for execution by a processor core. The execution speed of microprocessors is heavily analyzed and compared using standard benchmark tests for judging the performance of competing entries into the microprocessor market.
In processing circuits such as microprocessors, the comparison of multiple bits is a common and necessary operation but also a time consuming operation. Designs that accelerate multiple-bit comparison operations are continually sought. Timing is a common problem in multiple-bit comparison circuits because variable signal setup times may result depending on the signals that are applied to a comparator.
What is needed is a multiple-bit comparator and operating method that rapidly but accurately compares a multiple-bit signal.